Anyone who has studied electronics will undoubtedly have had to listen to an explanation of how a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) works, well here is a (somewhat) different explanation. The Marzipan On Surface Fairy-cake Éclair Technology version (bashed out by Datalas & Dooferlad), which makes sense (almost), also if you have studied electronics, you will (hopefully) notice that this explanation is pretty similar to what actually happens.
The Basic MOSFET is built with three éclairs (drain, gate and source) each is filled with cream, which is conductive (obviously). The éclairs are stuck in a bed of fairy-cake, the cake is coated by marzipan (ala batten burg cake) which (along with the cake) is non-conductive and prevents the cream from escaping (as marzipan should).
As more pressure is applied the cream gradually spreads out between the marzipan and fairy-cake, until it reaches the cream at both the source and drain éclairs.
When this happens (at threshold pressure) the source and drain éclairs are connected by a layer of conductive cream, enabling current to flow from the drain to source éclairs (conventional current that is)
When pressure is released from the gate éclair the weight of the marzipan squashes the cream layer, breaking the connection between source and drain.
Applying excessive amounts of cream, or pressure at either the drain or source will make little difference.
The original version (by me and Datalas) is available with pictures at http://www.datalas.com/funny/mosfet.html
A given MOSFET has 2 primary characteristics that dictate its behavior: it is either PMOS or NMOS, and either enhancement mode, or depletion mode. Enhancement mode devices tend to be more common, but PMOS and NMOS devices are often present in similar numbers in Complementary Metal-Oxide-Semiconductor (CMOS) devices (this is what the complementary portion stands for).
Enhancement Mode Depletion Mode | | | | ||---+ D ||---+ S ||---+ D ||---+ S | | | || || | G --||<--+ B G --||-->+ B G --||<--+ B G --||-->+ B | | | || | || ||---+ S ||---+ D ||---+ S ||---+ D | | | | Simplified (Current) Symbols: | | | | |---+ D |<--+ S ||---+ D ||<--+ S G --|| G --|| G --||| G --||| |-->+ S |---+ D ||-->+ S ||---+ D | | | | NMOS PMOS Logic (CMOS) Symbols: | | |--+ |--+ G -|| G -o|| |--+ |--+ | | NMOS PMOS
Here, G indicates the gate of the transistor, which controls current flow between S, the source of majority carriers and D, the drain. B indicates a body connection.
An NMOS Enhancement Mode MOSFET Trivial Circuit Gate Vdd | ___ Source | Drain | +------+ | +------- | | | MMMMMMMM+MMMMMMM | |---+ | | OOOOOOOOOOOOOOOO | +---|| | +-NN+NN-------------------NN+NN-+ | |-->+ | | NNNNN -channel- NNNNN | | | | | NNNNN NNNNN | + | | ^ | | | Vg (V) | | I | | | - | | | | | Body (P) | +--------+ | +---------------+---------------+ | | | --- ---+------------------+ /// Vss N = N-type material P = P-type material O = Oxide (insulator) layer M = Metal/Polysilicon layer
For the NMOS device pictured, connected as in the "trivial circuit", assume that Vg, the Gate voltage, equals 0. In this case, the Gate voltage is the same as the Source and Body voltage, also grounded (connected to Vss). That is:
Vg = Vs
The majority carrier in an NMOS device is the electron, possessing negative charge, and which can move freely through N-type material, but not through P-type material. In this situation, since the channel is composed of P-type body material, no current is allowed to flow (I = 0), and the device is off.
Now, suppose that Vg is increased past some level Vtn, which is called the threshold voltage (Vtn might be 1V). That is:
Vg - Vtn > Vs
Once the gate voltage has risen past this level, some of the negative charge carriers from the source and drain are attracted to the gate, effectively creating a channel of N-type material between the Source and Drain. Now, a negative (electron) current is able to flow through the channel from the source to the (higher voltage) drain: the transistor turns on.
I < 0
Now, the fact that there is a potential difference between the Drain and the Source means that the potential difference through the channel near the source side (Vg-Vs) is greater than the potential difference through the channel near the drain side (Vg - Vd, where Vd > Vs, thus Vg - Vd < Vg - Vs). This means that the channel is not as "deep" near the drain as near the source:
Gate | Source | Drain +------+ | +------- | | MMMMMMMM+MMMMMMM | | | OOOOOOOOOOOOOOOO | | +-NN+NNNNNNNNNNNNNNNNNNNNNNN+NN-+ | | NNNNNNNNNNNNNNNNNN NNNNN | | | NNNNN channel NNNNN | | | | | | | | | Body (P) | | +---------------+---------------+ | | ---+------------------+
In fact, the current through the channel is controlled by this potential difference, according to the following equation:
I = -(1/2)*(K'n)*(W/L)*(2*(Vg - Vtn - Vs)*(Vd - Vs) - (Vd - Vs)2) (NMOS Ohmic Region)
Where, K'n is the process parameter, the product of carrier mobility and gate capacitance, and (W/L) is the aspect ratio. (Typically, the aspect ratio can be modified by the designer of a CMOS Integrated circuit, while the process parameter cannot.)
If the drain voltage exceeds the Gate voltage by a large enough amount, the channel depth will drop to zero, and the channel will be in pinch-off. This occurs when Vg - Vtn < Vd. At this point, the device is said to be in Saturation, and no further increase the the Drain voltage will result in an increase in current. Thus, the current through the device is controlled solely by the Gate voltage, and the following equation applies:
I = -(1/2)*(K'n)*(W/L)*(Vg - Vtn - Vs)2 (NMOS Saturation Region)
PMOS devices operate analogously, except that the Gate voltage must be lower than the source voltage, and the source, drain, and channel are P-type material, while the body is N-type. Of course, the charge carrier in a PMOS transistor is not the electron, but the positively charged hole.
Depletion mode devices are different, in that, instead of creating (i.e. enhancing) a channel, the channel is already pre-existing, and one uses the gate to deplete the channel, cutting off current.
The MOSFET is the workhorse transistor of integrated circuits. While its analog properties are inferior to those of the bipolar junction transistor (BJT), its properties as a digital switch are superior. The microprocessors in our computers employ millions of MOSFET switches that perform arithmetic, store data, etc.
The basic function of a MOSFET in a digital circuit is to switch back and forth between a conducting state in which current is allowed to flow and an insulating state in which current is blocked. This switching between the two digital states (corresponding to binary 0 and binary 1) is controlled by the MOSFET gates. The clock speed of digital circuits is limited by how fast MOSFETs can switch back and forth. This switching corresponds physically to MOSFETs in conducting states charging or discharging the gate capacitors of other MOSFETs (and other parasitic capacitances).
There are many ways to make MOSFETs switch faster. Historically, the most important has been to make the gate length (i.e. the silicon channel length between the source and drain) smaller. As of 2002, this critical length is about 0.1 microns in state-of-the-art devices. One micron is one-thousandth of a millimeter. Such small devices are very difficult to fabricate and have required tremendous university and industry research. The fabrication of integrated circuits is a fascinating topic that is beyond the scope of this writeup. The fundamental obstacle to fabricating smaller MOSFETs is that photolithography cannot define structures smaller than 0.1 microns. New techniques--extreme ultraviolet lithography for instance--to replace photolithography are being investigated.
While new techniques are needed to fabricate smaller MOSFETs, the structure of MOSFETs must evolve as well. The most fundamental problem with today's structure is that as it shrinks to smaller than 0.1 microns, it cannot reach the insulating state--the switch never turns off. One solution to this problem is to fabricate circuits on silicon on insulator (SOI) wafers. Extremely small MOSFETs will require more exotic structures, such as that of the FINFET developed by the silicon device group at UC Berkeley.
Nobody has noded about how a MOSFET is fabricated. I will outline the standard bare-bones fabrication process. Obviously Intel incorporates several more process steps in the fabrication of transistors for a Pentium chip. All of the fabrication processes used are discussed in the node integrated circuit.
I will assume that wells and isolation have already been formed. After isolation, the wafer looks (in essence, not actuality) like this (see LOCOS):
_______ ___________ _________ | | | | | | | | Field |___________| Field |___________| Field oxide | | oxide | | oxide | Active | | Active | _______| area |___________| area |_________ Channel Channel Channel stop stop stop Doped silicon wafer (or well)
The MOSFETs will be created in the active areas and they will be isolated by the field oxide and channel-stop implantations.
The first step is to grow an ultrathin (the thinner the better down to about 1-2nm) gate-oxide layer on the silicon wafer. Next, a polysilicon gate (and interconnect) layer is deposited by chemical vapor deposition (CVD). The wafer now looks somewhat like this:
------- ----------- -------- Poly | |Polysilicon| | Poly | | | | _______ ----------- ___________ ----------- ________ |Polysilicon| |Polysilicon| | | | | Field |===========| Field |===========| Field oxide | | oxide | | oxide | Active | | Active | _______| area |___________| area |_________ Channel Channel Channel stop stop stop Doped silicon wafer (or well) ======= is the thin gate oxide
At this point lithography is used to define the gate. After photoresist is spun on the wafer and patterned, the polysilicon is etched by reactive ion etching (RIE). There is no reason to etch the thin oxide at this point. Now, the sources and drains of the MOSFETs are formed by ion implantation. The field oxide and polysilicon gate act as natural implantation masks. This is great! The gate, the sources and drains, and the isolation are all perfectly aligned by this process! The implanted ions easily go through the thin oxide above the source and drain regions.
The sources and drains are doped of opposite polarity to that of the wafer (or well). For example, if the wafer is p-type, the source and drain are doped n+, forming an NMOSFET. Since CMOS requires both n+ and p+ source and drains, it requires differently doped wells. The wafer looks like this after source/drain implantation:
_______ --- ___________ -- _________ | |Po | | | |Po | | | |ly | | | |ly | | Field |===========| Field |===========| Field oxide | S | | D | oxide | S | | D | oxide |___| |___| |___| |___| _______| |___________| |_________ Channel Channel Channel stop stop stop Doped silicon wafer (or well) ======= is the thin gate oxide S stands for source D stands for drain
Finally an oxide layer (sometimes called intermediate oxide) is deposited on top by CVD. This oxide is patterned by lithography and etched by RIE so that the sources and drains and the polysilicon gate are exposed. A metal layer such as aluminum is now deposited by sputtering to contact the gates and sources and drains. Actually, we can use the metal to interconnect the MOSFETs too. Voila, we've made a simple integrated circuit. More metal layers could be added if the integrated circuit is complex enough to require multiple interconnect layers, though a single interconnect layer is enough to do a whole lot of things on a chip.
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