| A SR Flip-Flop is the next evolutionary step up from the SR Latch. Instead of responding to input as long as the clock is high, the Flip-Flop responds only on the clock edge. That is, the state of the flip-flop can change only when the clock input changes.
One way to create a SR Flip-Flop is to use two SR Latches in a master-slave configuration:
+---------+ +---------+ clk S R | Y
S(H)--|S Y|---|S Y|---Y(H) _ ----+-------
| latch | | latch | _/_ 0 0 | rest
R(H)--|R Y|o--|R Y|o--Y(L) _/_ 1 0 | 1
| | | | _/_ 0 1 | 0
+-|C | +-|C | _/ 1 1 | *bad*
| +---------+ | +---------+
o |
/_\ |
| |
Clk-+-------------+
Be sure to see bistable multivibrator, and SR Latch for more details on how this works.
When the waveform on Clk is low, the values on S and R load into the first latch, the master, and this affects the outputs from the master stage; however, at this time, the slave is closed, and the values of the slave's output cannot change. Then, when Clk goes high, the master closes, and the slave opens, allowing the stored SR command from the master to ripple across. After a short delay, the proper value appears on the outputs Y(H) and Y(L).
In this case, the flip-flop responds to a rising edge on Clk. If the inverter were placed on the second latch instead of the first, the flip-flop would respond to a falling edge. In either case, the edge upon which the device triggers is called the active edge. In a flip-flop, there are a number of timing issues that need to be carefully examined. See setup time, hold time, propagation delay. Changing the inputs (S,R) during these times can result in metastability in the flip-flop.
See also D Flip-Flop, JK Flip-Flop, T Flip-Flop, synchronous sequential network, state machine, direct set, direct clear, synchronous design principles.
Also RS-Flip-Flop. | 
